reserves the right to change products or specifications without notice. N LY Programmable CAS (READ) latency (CL) 96-ball (8mm x 14mm) Rev. E HA for data, strobe, and mask signals 96-ball (7.5mm x 13.5mm) Rev. P DA 8 internal banks FBGA package (Pb-free) x16 Nominal and dynamic on-die termination (ODT) 96-ball (9mm x 14mm) Rev. N RG Differential clock inputs (CK, CK ) 78-ball (8mm x 10.5mm) Rev.
E RH 8n-bit prefetch architecture 78-ball (7.5mm x 10.6mm) Rev. Options Marking Features Configuration V = V = 1.35V (1.2831.45V) DD DDQ 1 Gig x 4 1G4 Backward compatible to V = V = 1.5V 0.075V DD DDQ 512 Meg x 8 512M8 Supports DDR3L devices to be backward com- 256 Meg x 16 256M16 patible in 1.5V applications FBGA package (Pb-free) x4, x8 Differential bidirectional data strobe 78-ball (9mm x 10.5mm) Rev.
MT41K256M16TW 107 XIT P DRIVER
Refer to DDR3 (1.5V) SDRAM Multipurpose register (Die Rev :E) data sheet specifications when running in Output driver calibration 1.5V compatible mode.
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